The present invention relates to telecommunication systems, and in particular, to radio transceiver systems and techniques.
Transceivers are used in wireless communications to transmit and receive electromagnetic waves in free space. In general, a transceiver comprises three main components: a transmitter, a receiver, and an LO generator or frequency synthesizer. The function of the transmitter is to modulate, upconvert, and amplify signals for transmission into free space. The function of the receiver is to detect signals in the presence of noise and interference, and provide amplification, downconversion and demodulation of the detected the signal such that it can be displayed or used in a data processor. The LO generator provides a reference signal to both the transmitter for upconversion and the receiver for downconversion.
Transceivers have a wide variety of applications ranging from low data rate wireless applications (such as mouse and keyboard) to medium data rate Bluetooth and high data rate wireless LAN 802.11 standards. However, due to the high cost, size and power consumption of currently available transceivers, numerous applications are not being fully commercialized. A simplified architecture would make a transceiver more economically viable for wider applications and integration with other systems. The integration of the transceiver into a single integrated circuit (IC) would be an attractive approach. However, heretofore, the integration of the transceiver into a single IC has been difficult due to process variations and mismatches. Accordingly, there is a need for an innovative transceiver architecture that could be implemented on a single IC, or alternatively, with a minimum number of discrete off-chip components that compensate for process variations and mismatches.
In one aspect of the present invention, a capacitor having two nodes includes a first transistor coupled to one of the two nodes, and a second transistor coupled to the first transistor and to a second one of the two nodes.
In another aspect of the present invention, an integrated circuit includes a capacitor having two nodes, a first transistor coupled to one of the two nodes, and a second transistor coupled to the first transistor and to a second one of the two nodes.
In yet another aspect of the present invention, a tunable capacitor array includes a plurality of capacitors each having first and second nodes, a first transistor coupled to the first node, and a second transistor coupled to the second node, the first nodes of the capacitors being coupled together and the second nodes of the capacitors being coupled together, and a plurality of switches each being positioned between a different one of the capacitors and the respective capacitors first or second node.
It is understood that other embodiments of the present invention will become readily apparent to those skilled in the art from the following detailed description, wherein it is shown and described only embodiments of the invention by way of illustration of the best modes contemplated for carrying out the invention. As will be realized, the invention is capable of other and different embodiments and its several details are capable of modification in various other respects, all without departing from the spirit and scope of the present invention. Accordingly, the drawings and detailed description are to be regarded as illustrative in nature and not as restrictive.